1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a support method for designing a layout of wiring lines of a semiconductor device.
2. Description of the Related Art
In a semiconductor device, there is a case that an upper limit is set for a resistance value of wiring lines for connection between macro cells. For example, an upper limit of the resistance value to power supply wiring lines for connection to analog circuit macro cells is set because of an analog property. Conventionally, as wiring line material, Al is used in many cases. In that case, in order to decrease the resistance value, a wiring line width is set relatively wide.
In recent years, as the wiring line material for a lower resistance value, Cu has been mainly introduced instead of Al. When Cu is used as the wiring line material, a phenomenon referred to as dishing is generated in a manufacturing process if the wiring line is designed to be wide. Specifically, at a CMP (Chemical Mechanical Polishing) step when a device is manufactured, a concave portion such as the shape of a dish is formed in the surface of the wide Cu wiring line. This implies the reduction in the flatness of the Cu wiring line and the reduction in a film thickness, and consequently leads to increase in the wiring line resistance.
In order to suppress the dishing, it is necessary at the designing stage to limit the wiring line width to a predetermined upper value or less. In order to meet the limit of the wiring line width and meet the upper limit of the resistance value, one wiring line may be considered to be divided into a plurality of thin wiring lines. For example, in FIG. 1, a power supply wiring line for connection between a first macro cell 101 and a second macro cell 102 is divided into a plurality of wiring lines 110 (hereafter, referred to as [Split Wiring Lines 110]). The plurality of split wiring lines 110 are a wiring line to send a same signal between the macro cells, and their potentials are all equal to each other. That is, the plurality of split wiring lines 110 can be collectively referred to as a bundle of wiring lines 111 to send a certain signal. Since the width W of each split wiring line 110 is limited, the dishing is suppressed. Also, the resistance value is decreased due to the bundle of wiring lines 111, thereby satisfying the limit on the resistance value.
The line width W of the split wiring line 110 is limited, and a certain limit is simultaneously imposed on a wiring line interval G between the split wiring lines 110. This is because a phenomenon of [Erosion] is caused in the manufacturing process if the wiring lines adjacent to each other are excessively close. The erosion is the phenomenon that an insulating film in a region where the wiring lines are dense is peeled together with Cu at the CMP step. Consequently, the side of the formed Cu wiring line is eroded, and the wiring line width W is made narrower than a design value. That is, similarly to the dishing, the erosion also brings about the increase in the wiring line resistance. Thus, at the designing stage, the wiring line interval G is required to be kept equal to or more than a predetermined limit (lower limit).
As the technique related to the wiring line design, a layout design method is disclosed in Japanese Laid Open Patent Application (JP-P2003-141200A) that is intended to attain a design so that a wiring line occupation rate satisfies a predetermined standard. According to the layout design method, slit wiring lines are firstly arranged. Next, a wiring line occupation rate in a certain area including the slit wiring lines is calculated. Next, in accordance with the wiring line occupation rate, a wiring line inhibition area is calculated such that the wiring line occupation rate error is never caused in the subsequent wiring line steps. Next, the wiring line inhibition area having a calculated area is provided in the foregoing certain area. Here, the position and shape of the wiring line inhibition area are arbitrarily set.
AT this time, the inventor of the present invention noted the following points. As mentioned above, in a layout design of the relatively thick wiring line such as a power supply wiring line and the like, the layout of the bundle of wiring lines 111 is executed in order to suppress dishing in a manufacturing process. Moreover, in order to protect erosion, a limit is imposed on an interval between the split wiring lines 110 of the bundle of wiring lines 111. A lower limit of the wiring line interval G is determined in accordance with the wiring line width W. For example, an upper limit of the wiring line width W is set to 1 μm, and the lower limit of the wiring line interval G is set to 1 μm.
In the layout design of the semiconductor device, an automatic layout of a usual signal wiring line 120 is executed after the arrangement of the bundle of wiring lines 111 whose resistance value is limited, as shown in FIG. 1. As this usual signal wiring line 120 (hereafter, referred to as a usual wiring line 120), a logic wiring line for connection between the macro cells is exemplified, and the resistance value is not especially limited. The usual wiring line 120 is desired to be thinner than the split wiring line 110. For example, the wiring line width of about 0.1 μm is desired. Thus, with regard to the usual wiring line 120, an intrinsic design standard different from that for the split wiring line 110 is defined, and a lower limit of the wiring line interval is set to be extremely smaller than the wiring line interval G of the split wiring line 110.
Therefore, when the automatic layout of the usual wiring line 120 is executed after the arrangement of the bundle of wiring lines 111, as shown in FIG. 1, there is a possibility that an automatic layout is executed, namely, the usual wiring line 120 is automatically laid in the area between the adjacent split wiring lines 110. In short, there is a possibility that the usual wiring line 120 of the same layer is automatically laid in the area for the bundle of wiring lines 111 laid in a certain wiring line layer. This fact finally results in the erosion. That is, although the bundle of wiring lines 111 is laid with effort for the dishing/erosion countermeasure, the automatic layout causes the final occurrence of the erosion. As mentioned above, the erosion causes the increase in the wiring line resistance.